Semiconductor on insulator devices are becoming more desirable as market demands continue to increase. SOI technology is becoming increasingly important for high performance thin film transistors (TFTs), solar cells, and displays, such as, active matrix displays, organic light-emitting diode (OLED) displays, liquid crystal displays (LCDs), integrated circuits, photovoltaic devices, etc. SOI structures may include a thin layer of semiconductor material, such as silicon, on an insulating material.
Various ways of obtaining SOI structures include epitaxial growth of silicon (Si) on lattice matched substrates, and bonding a single crystal silicon wafer to another silicon wafer. Further methods include ion-implantation techniques in which either hydrogen or oxygen ions are implanted either to form a buried oxide layer in the silicon wafer topped by Si in the case of oxygen ion implantation or to separate (exfoliate) a thin Si layer to bond to another Si wafer with an oxide layer as in the case of hydrogen ion implantation.
U.S. Pat. No. 7,176,528 discloses a process that produces an SOG (semiconductor on glass) structure using an exfoliation technique. The steps include: (i) exposing a silicon wafer surface to hydrogen ion implantation to create a bonding surface; (ii) bringing the bonding surface of the wafer into contact with a glass substrate; (iii) applying pressure, temperature and voltage to the wafer and the glass substrate to facilitate bonding therebetween; and (iv) separating the glass substrate and a thin layer of silicon from the silicon wafer.
The above approach is susceptible to an undesirable effect under some circumstance and/or when employed in certain applications. With reference to FIGS. 1A-1D, a semiconductor wafer 20 is implanted with ions, e.g., hydrogen ions, through a surface 21, such that the implantation dose is uniform in terms of density and depth across the semiconductor wafer 20.
With reference to FIG. 1A, when a semiconductor material, such as silicon, is implanted with ions, such as H-ions, damage sites are created. The layer of damage sites define an exfoliation layer 22. Some of these damage sites nucleate into platelets with very high aspect ratios (they have a very large effective diameter and almost no height). Gas resulting from the implanted ions, such as H2, diffuses into the platelets to form bubbles of comparably high aspect ratios. The gas pressure in these bubbles can be extremely high and has been estimated to be as high as about 10 kbar.
As illustrated by the bi-directional arrows in FIG. 1B, the platelets or bubbles grow in effective diameter until they get close enough to each other that the remaining silicon is too weak to resist the high pressure of the gas. As there is no preferential point for a separation front to start, the multiple separating fronts are randomly created and the multiple cracks propagate through the semiconductor wafer 20.
Near the edges of the semiconductor wafer 20, a larger share of implanted hydrogen may escape from the hydrogen rich plane. This is so because of the proximity of sinks (i.e., the side walls of the wafer 20). More particularly, during implantation, the ions (e.g., hydrogen protons) decelerate through the lattice structure of the semiconductor wafer 20 (e.g., silicon) and displace some silicon atoms from their lattice sites, creating the plane of defects. As the hydrogen ions lose their kinetic energy, they become atomic hydrogen and define a further, atomic hydrogen plane. Both the defect plane and the atomic hydrogen plane are not stable in the silicon lattice at room temperature. Thus, the defects (vacancies) and the atomic hydrogen move toward one another and form thermally stable vacancy-hydrogen species. Multiple species collectively create a hydrogen rich plane. (Upon heating, the silicon lattice cleaves generally along the hydrogen rich plane.)
Not all vacancies and hydrogen undergo collapse into hydrogen-vacancy species. Some atomic hydrogen species diffuse away from the vacancy plane and eventually leave the silicon wafer 20. Thus, some of the atomic hydrogen does not contribute to cleavage of the exfoliation layer 22. Near the edges of the silicon wafer 20, the hydrogen atoms have an additional path to escape from the lattice. Therefore, the edge areas of the silicon wafer 20 may be lower in hydrogen concentration. The lower concentration of hydrogen results in the need for a higher temperature or longer time to develop enough force to support separation.
Therefore, during the separation process, a tent-like structure 24 is created with edges that are not separated. At a critical pressure, fracture of the remaining semiconductor material occurs along relatively weak planes, such as {111} planes (FIG. 1C) and the separation of the exfoliation layer 22 from the semiconductor wafer 20 is complete (FIG. 1D). The edges 22A, 22B, however, are out of a major cleavage plane defined by the damage sites. This non-planar cleavage is not desirable. Other characteristics of the separation include that the exfoliated layer 22 can be described as having “mesas”, where the platelets or bubbles were, surrounded by “canyons”, where the fracture occurred. It is noted that these mesas and canyons are not accurately shown in FIG. 1D as such details are beyond the capabilities of reproduction at the illustrated scale.
Without limiting the invention to any theory of operation, the inventors of the instant application believe that the time from the onset of separation to completed separation is on the order of 10's of micro-seconds using the techniques described above. In other words, the random onset and propagation of the separation is on the order of about 3000 meters/sec. Again, without limiting the invention to any theory of operation, the inventors of the instant application believe that this rate of separation contributes to the undesirable characteristic of the cleaved surface of the exfoliation layer 22 described above (FIG. 1D).
U.S. Pat. No. 6,010,579 describes a technique of uniform ion implantation into a semiconductor substrate 10 to a uniform depth Z0, taking the wafer to a temperature below that which would initiate the onset of separation, and then introducing multiple impulses of energy to the edge of the substrate 10 in the vicinity of the implant depth Z0 in order to achieve a “controlled cleave front”. U.S. Pat. No. 6,010,579 states that the above approach is an improvement over so-called “random” cleavage at least as to surface roughness. The instant invention takes a directed separation approach that is significantly different from the “controlled cleave front” approach of U.S. Pat. No. 6,010,579 and different from the “random” cleaving approach.
The challenges associated with the separation of the exfoliation layer 22 from the semiconductor wafer 20 discussed above are exacerbated as the size of the SOI structure increases, and particularly when the shape of the semiconductor wafer is rectangular. Such rectangular semiconductor wafers may be used in applications where multiple semiconductor tiles are coupled to an insulator substrate. Further details regarding the manufacturing of a tiled SOI structure may be found in U.S. Application Publication No. 2007/0117354, the entire disclosure of which is hereby incorporated by reference.